FIG. 13 is a block diagram of a conventional clock data recovery circuit for non return-to-zero (NRZ) data. The conventional clock data recovery circuit has been described in, for example, “A Si Bipolar Phase and Frequency Detector IC for Clock Extraction up to 8 Gb/s” A. Pottbacker et., al. (IEEE Journal of Solid State Circuits, vol. SC-27, pp1747-1751 (1992)).
The conventional clock data recovery circuit shown in FIG. 13 includes a phase comparator 100, a low pass-filter (hereinafter, “LPF”) 200, a voltage control oscillator (hereinafter, “VCO”) 300, and a data identifier 400.
The phase comparator 100 compares input data DIN with a clock CLK1 generated by the VCO 300, and detects a difference between the phases of the two. The phase comparator 100 outputs a phase difference signal FEO1 to the LPF 200. The phase difference signal FEO1 corresponds to the detected phase difference in an analog value. The LPF 200 smoothes the phase difference signal FEO1 by removing a higher frequency component from this signal, thereby obtaining a voltage control signal, and outputs this voltage control signal to the VCO 300. The VCO 300 generates the clock CLK1 by adjusting an oscillation frequency based on the voltage control signal, and outputs the generated clock CLK1 to both the phase comparator 100 and the data identifier 400. The data identifier 400 identifies whether the input data DIN is “0” or “1” based on the clock CLK1 generated by the VCO 300.
FIG. 14 is a block diagram of the phase comparator 100 shown in FIG. 13. The phase comparator 100 includes a first sample holding circuit 110, a second sample holding circuit 120, and a selector 130.
The first sample holding circuit 110 samples a voltage of the clock CLK1 during a period when the input data DIN is high (“H”), and holds the voltage of the clock CLK1 at a fall of the input data DIN.
The second sample holding circuit 120 samples a voltage of the clock CLK1 during a period when the input data DIN is low (“L”), and holds the voltage of the clock CLK1 at a rise of the input data DIN.
The selector 130 selects an output SHO2 from the second sample holding circuit 120 when the input data DIN is “H”, and selects an output SHO1 from the first sample holding circuit 110 when the input data DIN is “L”. The selector 130 outputs the selected signal as the phase difference signal FEO1.
The operation of the conventional clock data recovery circuit is explained next. The operation of the phase comparator 100 is explained first with reference to a timing chart shown in FIG. 15. The timing chart in FIG. 15 indicates that a phase of the clock CLK1 generated by the VCO 300 is lagging behind a phase of the input data DIN. The input data DIN is NRZ data, which is input in the order of “H”, “L”, “L”, “H”, “L”, and “H”, that is, in the order of “1”, “0”, “0”, “1”, “0”, and “1”.
The first sample holding circuit 110 starts sampling the voltage of the clock CLK1 when the input data DIN changes from “L” to “H”. The second sample holding circuit 120 holds the voltage of the clock CLK1 at the moment when the input data DIN rises. During the period when the input data DIN is “H”, the selector 130 selects the output SHO2 from the second sample holding circuit 120, and outputs the selected output SHO2 from the second sample holding circuit 120 as the phase difference signal FEO1.
When the input data DIN changes from “H” to “L”, the first sample holding circuit 110 holds the voltage of the clock CLK1 at the moment when the input data DIN falls. The second sample holding circuit 120 starts sampling the voltage of the clock CLK1. During the period when the input data DIN is “L”, the selector 130 selects the output SHO1 from the first sample holding circuit 110, and outputs the selected output SHO1 from the first sample holding circuit 110 as the phase difference signal FEO1.
As explained above, the phase comparator 100 detects a phase difference between the phase of the input data DIN and the phase of the rising clock CLK1, at a change point (i.e., the rise or the fall) of the input data DIN. The phase comparator 100 outputs the detected phase difference information as the phase difference signal FEO1 in an analog value.
The operation of the conventional clock data recovery circuit is explained next. The phase comparator 100 compares the phase of the input data DIN with the phase of the clock CLK 1 generated by the VCO 300, and detects a phase difference between these two signals, as described above. The phase comparator 100 outputs the detected phase difference as the analog phase difference signal FEO1, to the LPF 200.
The LPF 200 smoothes the phase difference signal FEO1 by removing a higher frequency component from this signal, thereby obtaining a voltage control signal, and outputs this voltage control signal to the VCO 300. The VCO 300 generates the clock CLK1 by adjusting the oscillation frequency based on the voltage control signal. In other words, the VCO 300 adjusts the oscillation frequency based on the phase difference between the input data DIN at its change point and the clock CLK1 at its rise time, detected by the phase comparator 100. Based on this adjustment, the VCO 300 matches the phase of the input data DIN with the phase of the clock CLK1 at its rise time. The VCO 300 outputs the generated clock CLK1 to both the phase comparator 100 and the data identifier 400.
The data identifier 400 identifies whether the input data DIN is “1” or “0” at the fall of the clock CLK1. The data identifier 400 outputs the identified data as identification data. Since the same input data DIN signal is input to both the phase comparator 100 and the data identifier 400, the fall phase of the clock CLK1 generated by adjusting the oscillation frequency based on the voltage control signal coincides with the phase at the bit center of the input data DIN that is input to the data identifier 400. Therefore, when the input data DIN is identified at the fall of the clock CLK1, the data identifier 400 can identify the input data DIN at the bit center that is an optimum identification point of the input data DIN, as shown in FIG. 16A.
However, input data handled in the communication system is not limited to NRZ data. Assume that RZ data is input for the input data to the clock data recovery circuit according to the above conventional technique. The operation of the phase comparator 100 when the RZ data is input for the input data DIN is explained with reference to a timing chart shown in FIG. 17.
In the timing chart shown in FIG. 17, it is also assumed that the phase of the clock CLK1 generated by the VCO 300 is lagging behind the phase of the input data DIN and that RZ data “100101” is input for the input data DIN, like in the above example where the NRZ data is used for the input data DIN.
The first sample holding circuit 110 starts sampling the voltage of the clock CLK1 when the input data DIN changes from “L” to “H”. The second sample holding circuit 120 holds the voltage of the clock CLK1 at the moment when the input data DIN rises. During a period when the input data DIN is high (“H”), the selector 130 selects the output SHO2 from the second sample holding circuit 120, and outputs the selected output SHO2 from the second sample holding circuit 120 as the phase difference signal FEO1.
When the input data DIN changes from “H” to “L”, the first sample holding circuit 110 holds the voltage of the clock CLK1 at the moment when the input data DIN falls. The second sample holding circuit 120 starts sampling the voltage of the clock CLK1. During a period when the input data DIN is high (“L”), the selector 130 selects the output SHO1 from the first sample holding circuit 110, and outputs the selected output SHO1 from the first sample holding circuit 110 as the phase difference signal FEO1.
Since the phase of the clock CLK1 generated by the VCO 300 is lagging behind the phase of the input data DIN, when the input data DIN changes from “H” to “L”, the clock CLK1 remains at “H” at the moment when the input data DIN falls, as shown in FIG. 17. Therefore, the output SHO1 from the first sample holding circuit 110 and the output SHO2 from the second sample holding circuit 120 become different values.
When the input data DIN and the clock CLK1 are in a fixed phase relationship, the phase difference signal FEO1 as the output from the phase comparator 100 should also be fixed, in principle.
However, when the RZ data is input to the clock data recovery circuit according to the conventional technique, a disagreement occurs between a desired phase difference signal FEO1 indicated by a dashed line and a phase difference signal FEO1 actually output from the selector 130, as shown in FIG. 17.
When the phase of the clock CLK1 generated by the VCO 300 is lagging behind the phase of the input data DIN, the disagreement of the phase difference signal FEO1 lasts during the period when the input data DIN is “L”. In other words, the disagreement period of the phase difference signal FEO1 changes depending on the input data DIN.
As explained above, when the RZ data is input to the conventional clock data recovery circuit, the above disagreement occurs in the phase difference signal that is used to generate a clock for identifying data. Further, this disagreement period depends on input data. Therefore, the phase of the clock for identifying data is distorted, which makes it impossible to accurately identify the input data.
The present invention has been achieved in order to solve the above problems, and it is an object of the present invention to provide a clock data recovery circuit that can stably identify the input data of RZ data.